1. Field of the Invention
The present invention relates to methods of fabricating semiconductor integrated circuit devices, and more particularly, to methods of fabricating a silicon germanium layer on semiconductor integrated circuit devices and related semiconductor integrated circuit devices.
2. Description of the Prior Art In an attempt to improve the performance of semiconductor integrated circuit devices, many different techniques have been proposed to increase the speed of carriers flowing through a channel and/or to increase the density of electrons at the same carrier speed. For example, a technology has been proposed that forms a stress layer to provide a tensile stress to an n-type field effect transistor (nFET) region and to provide a compressive stress to a p-type field effect transistor (pFET) region. For pFET and eSiGe technology devices, silicon-germanium (SiGe) can be formed on an active region to apply a compressive stress to a channel using distortion that is created due to a difference in lattice length between silicon (Si) and germanium (Ge).
When forming a pFET active region using SiGe, it may be important to be able to grow SiGe without defects on a desired place and with a desired thickness. However, if the thickness of the grown SiGe is not uniform on the same wafer, different compressive stresses may be applied to channels of different semiconductor integrated circuit devices. The different compressive stresses may cause the semiconductor integrated circuit devices to have different performance characteristics, and may deteriorate the reliability of the semiconductor devices.